Live at Power-Up: PLD Effects on System Design
As systems become more complex, pressure to reduce cost and shorter design cycles are the drivers for higher efficiency, modularity, and simplicity of systems. When a certain feature is required in the application, designers usually scan the market for possible solutions that could meet system requirements. Once they narrow down the selection to those solutions that satisfy the design needs, they choose between the alternatives on the basis of cost and design simplicity.
This paper demonstrates how Level 0 live at power-up FPGAs address design requirements by serving applications that require short initialization time and instant availability of product features to the end user. Level-0 LAPU FPGAs make the system available to the microprocessor at power-up. Nonvolatile FPGAs can perform microprocessor address decoding, and the FPGA’s PLLs are immediately available. This leads to the elimination of external CPLDs, additional oscillator and reset handling circuitry, and results in an efficient and simplified system design.
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