Litho Aware Method for Circuit Timing/Power Analysis Through Process
Device extraction and the quality of device extraction is of increasing relevance to integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever-burgeoning demand of accurate device extraction. In this paper, we first present a method of extracting devices from layout, coupled with lithographic simulations. Then a complete flow for circuit time/power analysis using lithographic contours is described. Finally, comparisons between timing results from the conventional LVS method and Litho aware method are made in order to show the importance of litho contours considerations.
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