The old school of analog designers is fast becoming extinct, but the demand for analog/mixed-signal intellectual property (IP) blocks has never been greater. Many chips are being manufactured at 90-nm, and the ramp for 65-nm design starts has been more aggressive than expected. Following closely behind is 45-nm, with early versions of design rules and process parameters already available. The goal is to achieve improvements in digital speed, power, integration density, and ultimately lower cost, but the scaling of devices has led to some interesting challenges for the analog circuit designer.

This paper discusses these analog challenges and argues that they require a new breed of analog designer that can deal with the power dissipation constraints, device variability and model accuracy, and that can design methodology/tools for reliability.