The increasing density, functionality, and performance of each new FPGA generation delivers new design options for system architects faced with the daunting risks and costs associated with developing ASICs. Now that FPGAs offer performance and costs comparable to ASICs and ASSPs plus the additional advantages of low development risk, faster time to market, and flexibility, they are increasingly being used for critical system functions. As FPGAs displace ASICs and ASSPs, protecting designs implemented in FPGAs is becoming more important. This paper describes two techniques (configuration bitstream encryption and handshaking tokens) for securing designers’ intellectual property (IP) within SRAM-based FPGAs.