Layout Verification in the Era of Process Uncertainty: Target Process Variability Bands vs. Actual Process Variability Bands
There are several approaches being pursued for addressing runtime expectations in model-based physical verification with sufficient accuracy against current manufacturing processes. There is, however, a need for models that embed a contract with designers regarding realistic process control limits in a given technology for a particular layout. This is of particular importance in cases in which a process is still in development, as design and process development should progress in parallel with one another, and with a minimum risk of the design not yielding due to sub optimal layout configurations.
This paper presents several ideas as to how target process variability bands can be generated and discusses the limitations of actual process variability bands to meet such constraints. The paper aims to provide a perspective on the feasibility of providing target bands and on whether or not viable solutions will emerge in the future.
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