In today’s nanometer processes, the “layout pattern dependence” that causes variations in the electrical characteristics due to the shape around MOSFETs is becoming more significant. In response to this, NEC Electronics has introduced a highly accurate design environment that takes layout pattern dependence into consideration. For types of dependence not in the SPICE model, development was carried out to introduce a unique model. For neighboring active-area distance dependence (STI stress), the MIRAI-Selete development model was introduced, and for other types of dependence, independent development was carried out at NEC Electronics. This paper describes the development and calibration of these models that was applied to simulation during design using LVS rules that incorporate shape calculations derived by the ADP extraction feature of the Calibre nmLVS tool.

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