The never ending increase of silicon capacity available to system and IC designers, as predicted by Moore’s Law, brings on a cyclical crisis in design methodology and engineering productivity generating a ripple effect through the EDA and electronics industries. The System-on-a-Chip era will need more than available silicon to become a reality. A new design methodology roadmap based on IP reuse needs to emerge. Two of the EDA giants, Synopsys and Mentor Graphics, took the initiative at DAC 1997 to set the pace for the new challenge of System-on-a-Chip design. After more than a year and the publishing of the Reuse Methodology Manual (RMM) that sets the stage for IP Reuse and System-on-a-Chip design, where do we stand? The Reuse Methodology Manual is well perceived and accepted by the design community and represents a stake in the ground towards ensuring rapid creation of reusable designs. Throughout this tutorial an attempt is made to describe the total SoC design flow based on reusable IP and will also outline some non-trivial issues during this process: effect of available silicon capacity, SoC integration, SoC verification and documentation.

Note: By clicking on the above link, this paper will be emailed to your TechOnLine log-in address by Mentor Graphics.