Random Test Generation is commonly used for functional verification of semiconductor design. In this paper, the discussion is limited to processor verification while defining terminology and concepts relating to random test generation. Recent papers claim to have implemented a random test generator in a few weeks, whereas, experts in the field have spent millions. Random test generators can be implemented by one person in a few weeks, or can be implemented by a team over many years. If we assume both development teams are competent, then the papers must be presenting significantly different levels of random test generation capability. This paper’s goal is to provide a framework for comparing differing capabilities.

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