ModelSim provides an Integrated Debug Environment that facilitates efficient design debug for SoC and FPGA based designs. This GUI has continuously evolved to include new windows and support for new languages. This technical paper gives an introduction to the ModelSim 6.0 debug environment. The environment is trilingual, supporting designs based on VHDL, Verilog (all standards including SystemVerilog, Verilog 2001 and Verilog 1995), and SystemC.

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