Intel includes one or more SMBus controllers as part of their chipset devices. Its primary purpose is to permit the chipset to communicate with SMBus devices such as the SPD EEPROMs on the DIMMs, the clock driver, and various temperature sensors. Some designs incorporate I2C slave devices on the SMBus. Being "similar" to the I2C bus, it is often difficult to program the Intel SMBus controller to reliably communicate with these I2C slave devices.

The purpose of this paper is to provide details on the various SMBus cycles that the Intel SMBus controller can create, and then to provide guidelines on how to "analyze" the cycles supported by I2C devices to see if they can be successfully accessed by the Intel SMBus controller.