In this publication, we will describe and analyze simple, accurate and compact models for interconnect structures. These parameterized models are optimized for the particular fabrication process via field solver simulations and on wafer test structure measurements. Additionally, process variations will be incorporated in the compact models using the principal component analysis and performance response surface models to derive statistical interconnect models. A new test structure, along with the measurement scheme and the associated extraction methods are introduced here to facilitate the calibration of the interconnect models. Additionally, further tuning of those models with respect to measurements of complex on-chip test structures, such as clock nets, assures model accuracy and circuit performance predictability.

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