Various solutions exist for protection of virtual components (VCs), but not all are equally applicable to each type of VC. Trade-offs exist between the value (perceived or real) of the VC, difficulty of implementation of the protection scheme, and the resulting usability of the protected VC by both the integrator and the end user. This paper briefly discusses and introduces known technologies and mechanisms that support the broad spectrum of VC types, sources of VCs, and business requirements for VC users and providers.

The scope of this paper is to identify open, interoperable, standards-based solutions (or guidelines and information where standards are not practical) for VC protection which balance the level of security with customer usability of VCs, while fostering design reuse from creation through to the effective use of VCs. In this context, “VC” includes products, technology and software that may be protected through patents, copyrights or trade secrets. The trade-offs discussed can be used in selecting appropriate protection mechanisms for hard, firm and soft VCs.

The broad target audience for this paper includes VC providers, VC users (system designers or integrators), EDA vendors, and semiconductor vendors who utilize virtual components in standard product FPGA, CPLD, ASIC, or SoC market segments. Various protection, detection, and tracking mechanisms that can be employed with VCs and that are licensable to another party are discussed. This paper is concerned with protection of VCs and not with protection of design programs (EDA tools) used in processing them through a design flow.