Integration of Vera and System Studio
Every experienced system-on-chip (SoC) developer knows that there is no single technology that addresses all verification problems. Today’s complex SoC devices require a rich mix of RTL simulation, constrained-random testbenches, C-based models, verification IP, coverage metrics, equivalence checking and formal analysis for thorough verification. Recognizing this, Synopsys has integrated the key technologies in the Discovery Verification Platform.
Methodology is a critical part of Synopsys’ verification solution; users need to know how best to apply multiple verification technologies effectively and efficiently. Accordingly, Synopsys is always learning from its leading-edge customers—large and small—to understand which methodologies work best. What we learn filters back into our development and application teams, resulting in immediately useful new tool features, training and documentation.
This article provides an overview of a customer-driven methodology that accomplishes two key goals: enabling engineers to start developing the testbench earlier, before RTL is available, and providing a powerful solution to develop abstract architectural models of the SoC. The primary enabler for this methodology is the tight integration between two key elements of the Discovery Verification Platform: Vera and System Studio.
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