We present a new methodology for a balanced yield optimization and a new DFM framework which implements it. Our approach allows designers to dynamically balance multiple factors contributing to yield loss and select optimal combination of DFM enhancements based on the current information about the IC layout, the manufacturing process, and known causes of failures. The proposed methodology replaces the adhoc approach to DFM which targets one yield loss cause at a time at the expense of other factors with a comprehensive analysis of competing DFM techniques and tradeoffs between them.

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