The ability to iterate rapidly during the field programmable gate array (FPGA) design and debugging stages is critical for success. Designers want to reduce the compilation time for each design iteration, and feel confident that they can preserve their timing closure results to reduce the number of design iterations required to complete the design.


To address these concerns, a proven approach in ASIC design is now taking hold for FPGAs. FPGA and EDA vendors are offering incremental design and compilation capabilities previously available only with ASIC design tools. These capabilities include top-down methodologies that support design reuse, evolving designs, and engineering change orders, as well as bottom-up design methodologies that include team-based design flows. Altera’s Quartus II design software delivers incremental compilation to provide the productivity improvements demanded by today’s FPGA designers.


This white paper describes how an incremental compilation flow improves design productivity for high-density, high-performance FPGAs.