Increase Flexibility in Layer 2 Switches by Integrating Ethernet ASSP Functions Into FPGAs
A Layer 2 Ethernet switch connects multiple Ethernet LAN segments. Because each port on the switch can be connected to a different LAN segment, this topology forms a larger Ethernet network. The switch stores the media access controller (MAC) address—observed in frames received through each port—to identify each network segment. Using the MAC address, the switch forwards frames from the source segment to the destination segment only, instead of forwarding the frame to all the connected ports, consequently reducing network traffic.
ASSPs for multi-port Ethernet switches are widely available from different vendors and can be used to meet the requirements of a number of applications. However, these ASSPs are designed for “typical” networking applications and do not provide a good solution for applications that require specific features, such as a configuration of an odd number of ports or a configuration of ports of varying speeds. This paper describes how, with a low-cost, programmable logic-based architecture, a Layer 2 Ethernet switch can be implemented to address these needs, increase integration, and enable highly customized solutions compared to an architecture based on ASSPs.
Please disable any pop-up blockers for proper viewing of this Whitepaper.