Improving Verification Coverage of ARM SoCs While Reducing Simulation Runtime
Functional verification is one of the biggest challenges facing design teams today. The effort to fully verify a complex ASICs or ICs containing an ARM processor exceeds the design effort by a significant margin. Hundreds of imported and reused tests supplement a similar volume of newly crafted ones in an effort to detect and correct functional errors prior to tapeout. Yet over half of all first pass silicon undergoes a respin to correct logical or functional errors which escaped detection by functional verification. Better verification is clearly in order and an orthogonal approach may be more effective than writing more of the same style of test. Firmware is an effective functional supplement to testbenches whose intent is to verify hardware implementation.
A common reason for not utilizing firmware as a supplemental testbench is the time consumed simulating boot code, hardware diagnostics, and device drivers. As shown in various hardware/software co-verification tools the overall load on a simulation can be reduced by eliminating code and data references from the set of bus cycles generated by the processor model. These same techniques can be applied by hardware designers and verification engineers to use firmware, hardware diagnostics, and other software as a basis for creating functional verification tests. This software is often available from prior versions of the design or other groups on the design team. Simulation run-times can be reduced by partitioning the processor’s memory space between the logic simulation and the processor model.
Using an example we will detail this technique and present a commercially available tool, the Questa Verification Platform which automates the described methodology.
Please disable any pop-up blockers for proper viewing of this Whitepaper.