Improving Time to Design Closure with ISE Software
Timing closure is perhaps the single most important design issue facing designers today. With FPGAs and other deep submicron ICs, routing delays usually dominate logic delays. Although there are hundreds of ways to improve timing, such as using the embedded PowerPC™ processor or another high-speed core, the focus here is on improving performance on the logic and routing portion of the design. In this article, I will explore the methodology to achieve timing closure for Xilinx® designs.
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