Improving the Susceptibility of an Application to ESD-Induced Latch-up
All semiconductor devices are sensitive to electrostatic discharge (ESD) damage to varying degrees. This is true whether they are soldered to a PC board in an application, or whether they are unattached in the shipping or application assembly process. Good handling techniques such as groundstraps, static-free work stations and ionizers can reduce the risk of static build up during assembly. Often more attention is paid to reducing ESD during assembly than to reducing ESD risk during the lifetime of the application.
When a device is installed in an application, it is still susceptible to damage due to ESD. There is a great deal that the system designer can do to improve (by up to an order of magnitude) the level of protection of a device from latch-up inducing ESD
events. This tutorial is intended as a guide for helping
designers choose protection.
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