Improving the reliability and performance of RF ICs with advanced EDA technology
Radio frequency (RF) circuits are very sensitive to parasitic elements and layout-dependent effects, so both pre-and post-layout simulations are essential to ensuring a robust circuit that performs reliably over a broad range of operating conditions. But simulations are time-consuming and resource-intensive.
In this paper, learn about advanced electronic design automation (EDA) tools that provide enhanced verification and fill optimization that can drastically reduce the number of simulations required, while still ensuring designs will perform reliably in conformance with their design specifications over the lifetime of the products. This paper looks at:
- Design topology checking
- RF/Analog layout checking
- STI (shallow trench isolation) stress and well proximity effect (WPE)
- RF/Analog layout fill insertion
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