Layout vs. schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SOC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor. Full-chip LVS runs not only compare the design layout against the schematic netlist, but also typically include additional verification, such as electrical rule checking (ERC) and short isolation, that increase LVS runtimes.