With technology scaling, NAND devices suffer from high raw bit error rate (RBER) incurred by device physics variations at sub-20nm. At the same time, their error patterns also exhibit unbalanced characteristics. This paper proposes to fully utilize the error pattern characteristics abstracted from the NAND device to facilitate ECC decoding, so that we can simplify the NAND device design to reduce cost and/or improve the system’s overall reliability. It describes the ECC engine process flow. It also shows decoding gains under various flipping asymmetric bits.