NOR flash remains the preferred non-volatile technology for discrete memories in embedded systems. Today’s NOR based SPI memories have reached 108MHz clock rates with a QuadIO (x4) interface to achieve a 54MB/s sustained read throughput while remaining compatible with the original interface specified nearly 25 years ago. The legacy SPI interface and bus protocol is reaching fundamental timing limits that will make difficult further increases to the SPI bus clock rate. This paper will describe both system level and memory device strategies that deal with these timing limitations allowing higher SPI bus throughputs.