System Packet Interface Level 4 Phase 2 (SPI-4.2) is the Optical Internetworking Forum’s recommended interface for the interconnection of devices for aggregate bandwidths of OC-192 (ATM and POS) and 10 Gbps (Ethernet).

The SPI-4.2 interface has become the standard for interconnecting leading-edge 10 Gbps framers, traffic managers, network processors, and switch fabrics. SPI-4.2 is popular because of its efficient interface, which offers high bandwidth and low pin count, along with seamless handling of typical system requirements such as flow control, error detection, synchronization, and bus realignment.

The Xilinx Virtex-5 architecture provides an ideal platform for implementing SPI-4.2. The Xilinx SPI-4.2 LogiCORE IP targeting Virtex-5 devices provides a significantly smaller solution with dramatic power savings, 1.2 Gbps LVDS DDR I/O, and complete pin assignment flexibility.

Reprinted with permission from Xcell Journal / Fourth Quarter 2006. Article © Xcell Journal.