Power challenges in today’s IC designs create a significant increase in verification complexity. Critical design rule checking of variable spacing rules for densely packed multi-voltage nets is often verified with the traditional use of marker layers, a tedious and error-prone technique. Without an efficient means of verifying variable spacing within nets, designers often play it safe and simply apply maximum spacing throughout specific areas of a design, wasting valuable design area. Learn how to:

  • Optimize design size with correct voltage spacing rules
  • Avoid TDDB within your designs
  • Improve reliability and free yourself from manual marker layers