Implementing SystemVerilog for FPGA Design
SystemVerilog has experienced broad adoption in verification, but not until recently has it received much attention for its design constructs. The common explanation for this is that verification is the primary bottleneck in the design schedule; hence verification enhancements should logically be of the greatest interest. Recent studies show, however, that RTL implementation consumes nearly half of the design cycle, meaning that coding methodologies are far from perfect. SystemVerilog design constructs are intended to address the inefficiencies of conventional RTL design. This paper focuses on the set of the language’s constructs that raise the level of design abstraction to make RTL coding more intuitive, readable, and maintainable.
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