There are many challenges in implementing, efficient, high quality codecs with the limited resources available on low cost DSPs. This paper focuses on the main obstacles encountered in implementing an MPEG4 video codec on an embedded system that comprises of an Intel 80200 and a TI TMS320C6205 DSP. A proper platform data flow design, and platform specific optimizations can lead to massive performance improvements, over an initial nave approach to codec design. This will be shown with the implementation of a high quality, full frame rate (30fps) MPEG4 video codec. This paper will also discuss how the design of the hardware can lead to a high level of scalability, thus allowing the tailoring of the codec performance and quality to specific customer requirements.