The Memory Interface Generator (MIG) tool is a comprehensive tool used to simplify the design of memory controllers for Xilinx FPGAs. Memories are part of a majority of Xilinx applications. The goal of the MIG tool is to simplify memory interfaces, thus enabling FPGA users to focus on the rest of the system design.

The MIG tool was first introduced in 2002 as a memory controller pin selection utility for Virtex-II and Virtex-II Pro FPGAs. Since then, the MIG tool has progressed significantly; it now supports all Xilinx FPGA devices, including Virtex-4, Virtex-5, Spartan-3, and Spartan-3E FPGAs.

The MIG tool dynamically generates HDL in Verilog or VHDL formats based on user inputs. Additionally, the MIG tool generates .ucf pin constraints, any slice and logic placement constraints, and any other constraints required to create high-performance designs with minimal user changes. MIG outputs are fully available in nonencrypted formats. This enables you to modify the designs.

Reprinted with permission from Xcell Journal / Fourth Quarter 2006. Article © Xcell Journal.