Implementing Lowest Power Digital Datapaths in Days, not Weeks
Designing power and area optimal digital datapath blocks such as filters, modulators, demodulators, direct digital synthesizers (numerically controlled oscillators), forward and inverse transforms, and equalizers is expensive, highly resource intensive, and time consuming. Converging on optimal design is often infeasible.
Using GATeIC’s digital datapath design, optimization, and implementation tools on configurable IP solves the problem of optimizing power and area, while reducing cost and spec-to-GDSII time for ASICs, and minimizes resources on utilization FPGAs. ASIC implementations using GATeIC’s tools and IP, one in 180nm and another in 65nm, reduced power by 60% and 40%, and area by 30%.
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