Implementing Low-Cost DDR2 Interfaces with Spartan-3A FPGAs
Applications can generally be classified into two categories: high performance, where getting the highest bandwidth is paramount; and low cost, where the cost of the system is more important. However, not all systems are pushing memory performance limits. DDR SDRAMS and DDR2 SDRAMS, with data rates running below 400 Mbps per pin, are adequate for most low-cost systems. For these applications, Xilinx offers the Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3AN FPGAs.
This article describes the architecture of a DDR2 SDRAM memory interface implementation with Spartan-3 Generation FPGAs, and explains how Xilinx tools and hardware-verified reference designs can help you build your own memory interface.
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