Implementing DDR2 PCB Layout on the TMS320C6454/5
This application report contains implementation instructions for the DDR2 interface contained on the TMS320C6454/5 digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different from that of previous
devices. The previous approach specified device timing in terms of data sheet specifications and simulation models. The system designer was required to obtain compatible memory devices, as well as the device-specific data sheets and simulation models. This
information would then be used to design the printed circuit board (PCB) using high-speed simulation to close system timing.
For the C6454/5 DDR2 interface, the approach is to specify compatible DDR2 devices
and provide the PCB routing rule solution directly. TI has performed the simulation and system design work to ensure DDR2 interface timings are met. This report
describes the required routing rules.
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