This application report contains implementation instructions for the DDR2/mDDR interface contained on the TMS320DM35x Digital Media System-on-Chip (DMSoC) device. The approach to specifying interface timing for the DDR2/mDDR interface is quite different than on previous devices.

The previous approach specified device timing in terms of data sheet specifications and simulation models. The system designer was required to obtain compatible memory devices, as well as the device-specific data sheets and simulation models. This information would then be used to design the printed circuit board (PCB) using high-speed simulation to close system timing.

For the DM35x DDR2/mDDR interface, the approach is to specify compatible DDR2/mDDR devices and provide the PCB routing rule solution directly. TI has performed the simulation and system design work to ensure DDR2/mDDR interface timings are met. This document describes the required routing rules. The DM35x EVM provides an example of a PCB layout following these routing rules that passes FCC EMI requirements. You can copy the DDR2/mDDR portion of this layout directly, but the intent is to allow enough flexibility in the routing rules to meet other PCB requirements.