Reduction of power consumption in chips enables better, cheaper designs and minimizes power-related chip failures. This is leading designers to adopt increasingly sophisticated solutions; for example, instead of using a single supply net and voltage to power a design, designers often assign separate power nets to different blocks and step the power net voltage down wherever the chip and block performance allows. This technique is commonly referred to as “multi-voltage design,” and requires fundamental enhancements to a design methodology that must span the entire flow.

This paper explains multi-voltage and multi-supply power domain concepts, as well as the detailed requirements for designing within an advanced low-power, power-domain design flow.