Implementation of Digital Filters in Programmable Logic Devices
Recent strides in programmable logic density, speed, and hardware description languages (HDLs) have given the engineer the ability to implement digital signal processing (DSP) functionality within programmable logic devices (PLDs, or FPGAs). This paper provides an overview of general DSP concepts, filter design principles, and specific DSP filter architectures, as well as techniques for implementing DSP filters in FPGAs, using VHDL. Also covered are methods of exploiting specific FPGA architectures in order to enhance performance in terms of speed, area and power consumption. Finally, the paper provides the example of a specific IIR filter design implemented in an FPGA using VHDL.
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