Impact of sampling-clock spurs on ADC performance
This article shows that spurs on the ADC sampling clock can significantly degrade the overall system SFDR as well as the SNR. This effect gets amplified even more in undersampling applications where the signal input is moved to higher frequencies than those traditionally used for baseband input. It concludes that a filtered, high-quality sampling clock is necessary for system engineers who are trying to achieve maximum data converter performance.
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