The ability to reduce power consumption by up to a whopping 75 percent at the Electronic System Level (ESL)—a goal now proven reachable—has spawned new interest in solving power issues at that level. ESL is seen by many as the best opportunity to reduce the power consumed by a system. Power-optimizing tools that synthesize power-efficient architectures based on system-level power analysis achieve far greater power savings than possible with manual RTL design. And they do so before the architecture is locked in at the RT level. Moreover, this approach can be used prior to, and in addition to, power techniques at the RT level and below.