This paper offers a look at how Qualcomm optimized their integrated circuit (IC) design flows to achieve maximum efficiency. Using interactive and immediate signoff design rule checking (DRC) feedback, Qualcomm achieves critical milestones such as base layers and metal layers tapeouts inside the place and route (P&R) environment, providing more time to create innovative, high-quality designs that reach the market on or ahead of schedule.


Qualcomm Incorporated designs and markets wireless telecommunications products and services that are the foundational technologies that others build upon, from mobile processors to embedded platforms, Bluetooth products, and cellular modems. 

Faced with relentless advances in technology, the need for constant product innovation, and rapidly shifting markets, Qualcomm continually strives to optimize their IC design flows using the most effective level of resources. Achieving signoff design rule checking (DRC) convergence in digital implementation flows at advanced nodes is extremely challenging due to the number and complexity of the DRC rules, and the increasing functionality these designs contain. Traditionally, physical verification flows are set up for full-chip runs, and are not optimized for immediate DRC feedback on select design windows.