High-Speed SoC Simulation with ARM ESL Tools
Over recent years, there has been a growing realization that the complexity of modern System on Chip (SoC) designs benefits from early integration and simulation of hardware and software. At the very earliest phases of a project, system architects and concept engineers need to be able to evaluate alternative architectural and system design approaches—specifically bus structure (single-layer/multi-layer); system parameters (for instance, cache sizes); and overall system performance (for instance, hardware/software communication).
This article is derived from the Doulos Partner Course ‘ARM SoC Modelling with MaxSim’. It introduces the background to EDA ESL tools, in particular the use of high level abstraction in order to gain high simulation speed. It then looks at the underlying high-speed simulation model used within MaxSim Designer and MaxSim Explorer; and finally shows an example of a system model assembled using existing library components, and the display of performance and profiling information.
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