Designs for secure applications, such as smart cards and those used in the defense industry, require security to protect sensitive data. Conversely, scan chains have been used for decades to improve access to internal logic for automatic tester equipment (ATE) so that devices can be tested efficiently. This conflict in requirements has forced many designers of secure applications to use logic BIST and sacrifice test quality, or to perform deterministic scan tests in costly test environments.


Compunding these challenges are the ever-increasing requirements for high-quality test and additional test requirements for fabrication processes at smaller geometries. In this paper, we will explore techniques currently used for testing devices designed for secure applications, reviewing the benefits and limitations of each.

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