Programmable Logic Devices, such as field programmable gate arrays (FPGAs) are increasingly used in display systems to implement a variety of image processing functions. This increased usage is driven by the fast time-to-market and flexibility that programmable devices enable. Source synchronous interfaces within display systems, which send seven data bits for every cycle of the clock, are commonly used to transport image data. This approach has been used in devices such as the Texas Instruments Flat Linkl and National Semiconductor Channel Link devices. It has also been embodied in the Camera Link standard. System designers are looking to integrate these source synchronous interfaces within FPGAs. This paper presents details of the practical implementation of one of these interfaces in a low-cost FPGA. Details of the design approach and results are included.