High-Performance ADCs with Interfacing, Driving and Clocking Schemes
The performance of integrated, high-speed pipeline analog-to-digital converters (ADCs) is reaching new heights and pushing the limits of resolution, sampling speed, and dynamic performance. However, designers must select components around the converter very carefully, in order to keep static and dynamic performance at the levels given in the datasheet. This application note introduces National Semiconductor’s ADC14V155, and discusses how the performance of high-speed pipeline ADCs can be optimized by designing the right clock circuitry and a good analog input network, as well as how to get the data at these high speeds undistorted from an ADC onto an FPGA or ASIC.
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