During full-chip timing closure, we need to do the timing analysis of the entire design at the device top level to find out the chip interface timings and the block to block interconnect timings. But we can not do this straightaway in one shot, especially in case of bigger and complex designs. It becomes very difficult to iterate the timing analysis procedure for the full-chip, especially for a bigger design and it takes lot of time to converge not only in terms of run-time and memory footprint, but also based on the stage and progress of the design.

In this paper, we will discuss about the concept of hierarchical timing closure, reasons behind choosing hierarchical approach over flat, use of timing models, different phases of timing closure and various time budgeting principles and algorithms.