HD Video Encoding with DSP and FPGA Partitioning
As video and imaging applications evolve toward high-definition (HD) video compression standards, co-processing architectures that include both digital signal processors (DSPs) and field programmable gate arrays (FPGAs) are becoming a more popular solution. These partitioned systems are not the only option, however; new advances in DSP architectures, performance, peripheral mix, video hardware acceleration, and implementation techniques have significantly
broadened the range of applications in which DSPs can provide a complete solution.
This paper explains how developers can now employ a new generation of DSPs for video and imaging applications, such as Texas Instruments’ TMS320C6455 DSP with a Serial RapidIO (SRIO) bus, which has integrated several high-speed peripherals.
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