Hardware/Software Validation with a TLM Virtual System Prototype
Today’s consumer electronics applications are not only extremely cost and schedule-sensitive, but are also among the most challenging to create. Starting application software and firmware development against a high-level hardware model can save significant development time and yield better products. There is therefore a pressing need for earlier hardware/software (HW) validation.
A new system design methodology is emerging in response to this need. The approach is based on a scalable transactional level modeling (TLM) concept that describes the hardware in SystemC, and allows software teams to use it as a development platform at the earliest stages of hardware design. This paper describes this new approach to HW verification and the resulting integration of hardware and software development, as well as selecting the appropriate TLM verification methods for your purposes.
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