Getting Closer to a Top-Down Methodology for RF SoC Design
The drive to fully integrate communication products onto a single chip has created the urgent need for an integrated RF SoC design flow. Until now the EDA community has not managed to assemble a satisfactory integrated flow for mixed-signal RF because no single vendor has offered all the necessary technologies. Vendors have tried to use co-simulation to achieve this, but co-simulation seriously complicates the designer’s life – even preparing the design for simulation is far harder this way and co-simulation is intrinsically slower, less stable and subject to conflicting clock problems. Even if you have all the technologies, integrating them into a single kernel solution is an enormous task, which Mentor Graphics engineers have been working on for about seven years. The good news is that an integrated single kernel solution is now available.
In this paper we will explain an effective RF SoC flow using a tightly integrated custom IC design environment which combines with functional and physical verification tools and foundry-specific design kits to solve the RF SoC problem.
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