In digital design, applying a master reset for all flip-flops is standard practice. Inserting a reset, however, is in fact not crucial, and may unnecessarily impact
development time and product costs.


A design implemented in a Xilinx field programmable gate array (FPGA) does not require insertion of a global reset network. For the vast majority of any design, the initialization state of all flip-flops and random access memory (RAM) following configuration is more comprehensive than any logical reset will ever be. There is no requirement to insert a reset for simulation because nothing will be undefined.


This paper explains why the parts of a system that truly need to be reset must be identified and why the release of those resets on start-up or during operation must be controlled as carefully as any other signal within a synchronous circuit.