Functional Verification Automation for IP
The development and integration of intellectual property (IP) in the form of large functional blocks, or cores, is an essential part of an increasing number of today’s IC design strategies. Numerous benefits justify this approach. Properly managed, the use of pre-designed, pre-verified IP blocks can cut man-months off the design cycle, provide opportunities for design reuse in future systems, and where applicable, ensure compliance with complex standards and protocols.
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