FPGAs Go, Go, Go: Solving FPGA Timing Closure for High Speed Designs
This paper outlines Dillon Engineering’s guidelines for success in implementing complete radar processing algorithms on a single multi-million gate FPGA. Most of these systems involve FFT processing along with other DSP algorithms. Dillon has recently implemented several radar processing systems on single FPGAs, and attributes this success in large part is due to its ability to reuse IP as well as the reliability of the tools available in its design flow.
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