FPGA Run-Time Reconfiguration: Two Approaches
Run-time reconfiguration is defined as the ability to modify or change the functional configuration of a device during operation, through either hardware or software changes. This is a field programmable gate array (FPGA) feature that is important to communications, military, and consumer applications as an approach to reducing component count and power consumption, by re-using the same FPGA for several functions.
This white paper examines two approaches to run-time reconfiguration. FPGA partial reconfiguration (PR) is a Xilinx design flow that attempts to create reconfiguration regions in an FPGA device, so that one region can be reconfigured while the remainder of the FPGA continues to operate in system. Software programmable reconfiguration (SPR) is the designed-in capability to modify digital logic flows through internal or external software commands.
Please disable any pop-up blockers for proper viewing of this Whitepaper.