This report presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as the Rijndael Algorithm), selected as New Algorithm by the National Institutes of Standards and Technology (NIST). We have implemented the AES encryption decryption algorithm on the FPGA. Our design mainly concentrates on the speed up along with area optimization. Our work-steps includes Paper Designing of fully pipelined hardware architecture for AES Algorithm, Writing VHDL Code for the said algorithm, Simulating the code on “ModelSim SE PLUS 5.8b”, Synthesizing and Implementing the code on “Xilinx – Project Navigator, ISE” with Device XC2V6000 of Vertex II Family and XST Synthesis Tool and finally we have implemented on ALPHA DATA board.